AD6624AS datasheet(28/40 Pages) AD

28 / 40 page

REV. B

AD6624

–28–

Table VIII. Channel Address Memory Map (continued)

Ch Address

Bit Width

Comments

BIST Signature for I Path

BIST-I

BIST Signature for Q Path

BIST-Q

# of BIST Outputs to Accumulate

19–0: # of Outputs (Counter Value Read)

RAM BIST Control Register

D-RAM Fail/Pass

C-RAM Fail/Pass

RAM BIST Enable

Serial Port Control Register

Map RCF Data to BIST Registers

8–7:

I_SDFS Control

1x:

Separate I and Q SDFS Pulses

01:

SDFS High for Entire Frame

00:

Single SDFS Pulse

6–5:

SOWL

1x:

24-Bit Words

01:

16-Bit Words

00:

12-Bit Words

SBMx

3–0:

SDIVx[3:0]

SCLK

SDI

DATA

tSSI

tHSI

Figure 39. Serial Input Data Timing Requirements

SCLK

SDO

I15

I14

tDSDO

I13

Figure 40. Serial Output Data Switching Characteristics

SCLK

SDFS

tSSF

tHSF

Figure 41. SDFS Timing Requirements (SBM = 0)

SDO

IMSB

SDFS

SCLK

tDSO

IMSB1

SDFS MINIMUM

WIDTH IS ONE SCLK

FIRST DATA IS AVAILABLE THE FIRST

RISING SCLK AFTER SDFS GOES HIGH

Figure 42. Timing for Serial Output Port (SBM = 1)

SCLK

SDFS

SDFE

tDSDFS

tDSDFE

Figure 43. Serial Frame Switching Characteristics (SBM = 1)

SCLK

SDO

SDFE

tDSDO

tDSDFE

I14

I15

Figure 44. SDO, SDFE Switching Characteristics

SBM0

SBM0 is the Serial Bus Master pin for the Channel 0 Serial Port

only. Serial Ports 1, 2, and 3 will always default to Serial Slave

mode but can be programmed as masters in the internal register

space. The SBM0 pin gives the user the option to boot the

AD6624 through Serial Port 0 as a master. When SBM0 is high

(master mode), the AD6624 generates SCLK0 and SDFS0.

When SBM0 is low (slave mode), the AD6624 accepts external

SCLK0 and SDFS0 signals. When configured as a bus master,

the SCLK0 signal can be used to strobe data into the DSP inter-

face. When used with another AD6624 in Serial Cascade mode,

SCLK0 can be taken from the master AD6624 and used to shift

data out from the cascaded device. In this situation, SDFS of

the slave AD6624 channel is connected to the SDFE pin of the

master AD6624 channel (or the preceding chip in the chain).

When an AD6624 is in Serial Slave mode, all of the serial port

activities are controlled by the external signals SCLK and SDFS.

AD6624AS 데이터시트(PDF) 28 Page - Analog Devices

AD6624AS 데이터시트(HTML) 28 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

데이터시트 다운로드

링크 URL