4LS datasheet(64/115 Pages) AMSCO

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4LS

Datasheet

• PUBLIC

DS000542

• v3-01 • 2022-Nov-17

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│ 63

Address: 0x03

Default Value: 0x00

Access: Read/Write

Bit

Bit Name

Default

Bit Description

4:4

Top Bottom

Connection

When set to ‘1’ connects the analogue

reference signals between Top and

Bottom elements.

Signals connected when this bit is high:

ADC gain ref input, ADC gain ref output,

VREF (CDS reference voltage), VBL

(ADC offset - black level voltage).

3:3

Gain CDS L2

When set to ‘1’ defines the analogue gain

on the CDS stage to be 2x.

2:2

Gain CDS L1

When set to ‘1’ defines the analogue gain

on the CDS stage to be 2x.

1:1

CVC L2 Full Well

Capacity

When ‘0’ and Gain CDS L2 = ‘1’ the Full

Well Capacity is 10 ke-

When ‘0’ and Gain CDS L2 = ‘0’ the Full

Well Capacity is 20 ke-

When ‘1’ and Gain CDS L2 = ‘0’ the Full

Well Capacity is 40 ke-

0:0

CVC L1 Full Well

Capacity

When ‘0’ and Gain CDS L1 = ‘1’ the Full

Well Capacity is 10 ke-

When ‘0’ and Gain CDS L1 = ‘0’ the Full

Well Capacity is 20 ke-

When ‘1’ and Gain CDS L1 = ‘0’ the Full

Well Capacity is 40 ke-

9.1.5

Analogue Gain for Line 1 Register (Address 0x04)

Figure 95:

AGL1Reg

Address: 0x04

Default Value: 0x80

Access: Read/Write

Bit

Bit Name

Default

Bit Description

7:0

Analogue Gain Level

10000000b

It defines the analogue gain level in the

ADC which defines the voltage equivalent

to one ADC step (1 DN) applied to the

Line 1.

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