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4LS 데이터시트(PDF) 80 Page - ams AG

부품명 4LS
상세설명  4LS15K, 4LS10K and 4LS5K Line Scan Sensors
PDF  115 Pages
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제조업체  AMSCO [ams AG]
홈페이지  http://www.ams.com
Logo AMSCO - ams AG

4LS 데이터시트(HTML) 80 Page - ams AG

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4LS
Register Description
Datasheet
• PUBLIC
DS000542
• v3-01 • 2022-Nov-17
114
│ 79
Address
Register ID and Description
Default
Value
0x1C
RRQReg
– Sets the address of the register to be read on a read back
operation
0x00
0x1D
STS4Reg- Holds several configuration bits
0x49
0x1E
STS5Reg- Holds several configuration bits
0x30
0x1F
STS6Reg- Holds several configuration bits
0x05
The figure below shows the values of the recommend registers that can be applied to all segments.
Figure 135:
Recommended Sensor Register Setting(1)
Address
Register ID and Description
Recommended Value
0x01
STS1Reg
– Holds several configuration bits
0x19(2)
0x02
STS2Reg
– Holds several configuration bits
0x00(3)
0x0B
PBCReg
– Sets the current provided by the bias block
0x31
0x0C
PLVDReg
– Sets the current used on LVDS driver
0x9D(4)
0x1D
STS4Reg- Holds several configuration bits
0x48
0x1E
STS5Reg- Holds several configuration bits
0x30(5)
0x1F
STS6Reg- Holds several configuration bits
0x35
(1)
The referred registers are the relevant ones for a stable startup and normal sensor operation.
(2)
See the recommended startup sequence recommendation (Section 7.2). Will have different value if using ROI for
4LS5K.
(3)
Dependently of Readout mode, ADC mode and MCLK frequency, the user must use the respective register value.
(4)
Increase the LVDS bias current for a better signal detection.
(5)
This CLK phase configuration is specific for the ams OSRAM test system. CLK phase for PLL clock compensation
should be chosen according to the user hardware, in order to have stable sensor operation.



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