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AD9510-VCO/PCB 데이터시트(PDF) 47 Page - Analog Devices

부품명 AD9510-VCO/PCB
상세설명  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
PDF  60 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD9510-VCO/PCB 데이터시트(HTML) 47 Page - Analog Devices

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AD9510
Rev. A | Page 47 of 60
Addr
(Hex)
Parameter
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Def.
Value
(Hex)
Notes
3A
Delay Fine
Adjust 6
Not Used
5-Bit Fine Delay <5:1>
Not
Used
00
Min. Delay
Value
3B
Not Used
04
OUTPUTS
3C
LVPECL OUT0
Not Used
Output Level
<3:2>
Power-Down <1:0>
0A
OFF
3D
LVPECL OUT1
Not Used
Output Level
<3:2>
Power-Down <1:0>
08
ON
3E
LVPECL OUT2
Not Used
Output Level
<3:2>
Power-Down <1:0>
08
ON
3F
LVPECL OUT3
Not Used
Output Level
<3:2>
Power-Down <1:0>
08
ON
40
LVDS_CMOS
OUT 4
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02
LVDS, ON
41
LVDS_CMOS
OUT 5
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
02
LVDS, ON
42
LVDS_CMOS
OUT 6
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
03
LVDS, OFF
43
LVDS_CMOS
OUT 7
Not Used
CMOS
Inverted
Driver On
Logic
Select
Output Level
<2:1>
Output
Power
03
LVDS, OFF
44
Not Used
CLK1 AND
CLK2
Input
Receivers
45
Clocks Select,
Power-Down
(PD) Options
Not Used
CLKs in
PD
REFIN PD
CLK
to
PLL
PD
CLK2
PD
CLK1
PD
Select
CLK IN
01
All Clocks
ON, Select
CLK1
46, 47
Not Used
DIVIDERS
48
Divider 0
Low Cycles <7:4>
High Cycles <3:0>
00
Divide by 2
49
Divider 0
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
4A
Divider 1
Low Cycles <7:4>
High Cycles <3:0>
00
Divide by 2
4B
Divider 1
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
4C
Divider 2
Low Cycles <7:4>
High Cycles <3:0>
11
Divide by 4
4D
Divider 2
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
4E
Divider 3
Low Cycles <7:4>
High Cycles <3:0>
33
Divide by 8
4F
Divider 3
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
50
Divider 4
Low Cycles <7:4>
High Cycles <3:0>
00
Divide by 2
51
Divider 4
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
52
Divider 5
Low Cycles <7:4>
High Cycles <3:0>
11
Divide by 4
53
Divider 5
Bypass
No
Sync
Force
Start H/L
Phase Offset <3:0>
00
Phase = 0
54
Divider 6
Low Cycles <7:4>
High Cycles <3:0>
00
Divide by 2



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