AD9513SLASHPCB datasheet(8/28 Pages) AD

8 / 28 page

AD9513

Rev. 0 | Page 8 of 28

CLOCK OUTPUT ADDITIVE TIME JITTER

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVDS OUTPUT ADDITIVE TIME JITTER

Calculated from SNR of ADC method

CLK= 400 MHz

300

fs rms

LVDS (OUT0) = 100 MHz

Divide Ratio = 4

LVDS (OUT1, OUT2) = 100 MHz

Interferer

CLK = 400 MHz

300

fs rms

LVDS (OUT0) = 100 MHz

Divide Ratio = 4

LVDS (OUT1, OUT2) = 50 MHz

Interferer

CLK = 400 MHz

305

fs rms

LVDS (OUT1) = 100 MHz

Divide Ratio = 4

LVDS (OUT0, OUT2) = 100 MHz

Interferer

CLK = 400 MHz

310

fs rms

LVDS (OUT1) = 100 MHz

Divide Ratio = 4

LVDS (OUT0, OUT2) = 50 MHz

Interferer

CLK = 400 MHz

310

fs rms

LVDS (OUT2) = 100 MHz

Divide Ratio = 4

LVDS (OUT0, OUT1) = 100 MHz

Interferer

CLK = 400 MHz

315

fs rms

LVDS (OUT2) = 100 MHz

Divide Ratio = 4

LVDS (OUT0, OUT1) = 50 MHz

Interferer

CLK = 400 MHz

345

fs rms

LVDS (OUT2) = 100 MHz

Divide Ratio = 4

CMOS (OUT0, OUT1) = 50 MHz

Interferer

CMOS OUTPUT ADDITIVE TIME JITTER

Calculated from SNR of ADC method

CLK = 400 MHz

300

fs rms

CMOS (OUT0) = 100 MHz

Divide Ratio = 4

LVDS (OUT2) = 100 MHz

Interferer

CLK = 400 MHz

300

fs rms

CMOS (OUT0) = 100 MHz

Divide Ratio = 4

CMOS (OUT1, OUT2) = 50 MHz

Interferer

CLK = 400 MHz

335

fs rms

CMOS (OUT1) = 100 MHz

Divide Ratio = 4

CMOS (OUT0, OUT2) = 50 MHz

Interferer

CLK = 400 MHz

355

fs rms

CMOS (OUT2) = 100 MHz

Divide Ratio = 4

CMOS (OUT0, OUT1) = 50 MHz

Interferer

CLK = 400 MHz

340

fs rms

CMOS (OUT2) = 100 MHz

Divide Ratio = 4

LVDS (OUT0, OUT1) = 50 MHz

Interferer

AD9513/PCB 데이터시트(PDF) 8 Page - Analog Devices

AD9513/PCB 데이터시트(HTML) 8 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

데이터시트 다운로드

링크 URL