AD9880SLASHPCB datasheet(44/64 Pages) AD

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AD9880

Rev. 0 | Page 44 of 64

0x23

7-0

Hsync Duration

An 8 bit register that sets the duration of the Hsync

output pulse. The leading edge of the Hsync output is

triggered by the internally generated, phase-adjusted

PLL feedback clock. The AD9880 then counts a

number of pixel clocks equal to the value in this

output, which is also phase-adjusted. The power-up

default is 32.

0x24

Hsync Output Polarity

This bit sets the polarity of the Hsync output. Setting

this bit to 0 sets the Hsync output to active low. Setting

this bit to 1 sets the Hsync output to active high.

Power-up default setting is 1.

Table 41. Hsync Output Polarity Settings

Hsync Output Polarity Bit

Result

Hsync output polarity negative

Hsync output polarity positive

0x24

Vsync Output Polarity

This bit sets the polarity of the Vsync output (both

DVI and analog). Setting this bit to 0 sets the Vsync

output to active low. Setting this bit to 1 sets the Vsync

output to active high. Power-up default is 1.

Table 42. Vsync Output Polarity Settings

Vsync Output Polarity Bit

Result

Vsync output polarity is negative

Vsync output polarity is positive

0x24

Display Enable Output Polarity

This bit sets the polarity of the display enable (DE) for

both DVI and analog.

Table 43. DE Output Polarity Settings

DE Output Polarity Bit

Result

DE output polarity is negative

DE output polarity is positive

The power-up default is 1.

0x24

Field Output Polarity

This bit sets the polarity of the field output signal on

Pin 21. The power-up default setting is 1.

Table 44. Field Output Polarity

Select

Result

Active low = even field; active high = odd field

Active low = odd field; active high = even field

Output field polarity (both DVI and analog)

0 = active low out

1 = active high out

The power-up default is 1.

0x24

SOG Output Polarity

This bit sets the polarity of the SOGOUT signal

(analog only).

Table 45. SOGOUT Polarity Settings

SOGOUT

Result

Active low

Active high

The power-up default setting is 1.

0x24

2-1

SOG Output Select

These register bits control the output on the SOGOUT

pin. Options are the raw SOG from the slicer (this is

the unprocessed SOG signal produced from the sync

slicer), the raw Hsync, the regenerated sync from the

sync filter, which can generate missing syncs because

of coasting or drop-out, or the filtered sync that

excludes extraneous syncs not occurring within the

sync filter window.

Table 46. SOGOUT Polarity Settings

SOGOUT Select

Function

Raw SOG from sync slicer (SOG0 or SOG1)

Raw Hsync (Hsync0 or Hsync1)

Regenerated sync from sync filter

Hsync to PLL

The power-up default setting is 11.

0x24 0

Output Clock Invert

This bit allows inversion of the output clock as

specified by Register 0x25, Bits 7 to 6. The power-up

default setting is 0.

Table 47. Output Clock Invert

Select

Result

Noninverted clock

Inverted clock

0x25

7-6

Output Clock Select

These bits select the clock output on the DATACLK

pin. They include 1/2× clock, a 2× clock, a 90° phase

shifted clock or the normal pixel clock. The power-up

default setting is 01.

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