AD9923ABBCZRL datasheet(45/88 Pages) AD

45 / 88 page

AD9923A

Rev. 0 | Page 45 of 88

XV7

V7B

VSG8

Figure 61. XV7, VSG8, and V7B Output Polarities

XV2, XV4, XV6, XV8

XV9, XV10, XV13

V2, V4, V6, V8

V9, V10, V13

Figure 62. XV2, XV4, XV6, XV8, XV9, XV10, XV13 and V2, V4, V6, V8, V9, V10, V13 Output Polarities

XSUBCNT

SUBCK

XSUBCK

VMM

VLL

Figure 63. XSUBCNT, XSUBCK, and SUBCK Output Polarities

SHUTTER TIMING CONTROL

The CCD image exposure time is controlled by the substrate clock

signal (SUBCK) that pulses the CCD substrate to clear out

accumulated charge. The AD9923A supports three types of

electronic shuttering: normal, high precision, and low speed.

Together with the SUBCK pulse placement, the AD9923A can

accommodate different readout configurations to further

suppress the SUBCK pulses during multiple field readouts. The

AD9923A also provides programmable outputs to control an

external mechanical shutter (MSHUT), strobe/flash (STROBE),

and CCD bias select signal (VSUB). Up to four general shutter

pulses (SHUT0 to SHUT3) and two VSUB pulses (VSUB0 and

VSUB1) can be programmed and assigned to any of the three

shutter output pins. The user can also combine the following

shutter and VSUB pulses with a logic XOR operation (symbolized

by ^) to generate more complex timing (up to four toggle posi-

tions per line) for MSHUT, STROBE and VSUB: SHUT0 ^ VSUB0,

SHUT0 ^ VSUB1, SHUT0 ^ SHUT1, and SHUT0 ^ SHUT2.

SUBCK: Three-Level Output

The AD9923A supports a three-level output from the SUBCK

buffer: VH, VMM, and VLL. The VH power supply is shared

with the V-driver outputs, but VMM and VLL are dedicated

mid and low supplies for the SUBCK buffer. There are two in-

puts to the SUBCK buffer, XSUBCK and XSUBCNT. XSUBCNT

is created by an internal multiplexer that selects from XV1 to

XV13, VSG1 to VSG8, MSHUT, STROBE, VSUB, SHUT0 to

SHUT3, FG_TRIG, high and low.

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