Note 4: Spec. is guaranteed by design.

Note 5: Measured from rising-edge of first SDI cycle until Lock Detect bit goes high (true). Lock time includes CDR phase acquisition time plus PLL lock time.

conditions.

Note 7: When used to clock control data into or from the CLC031, the duty cycle restriction does not apply.

Note 9: Required Input Conditions are the electrical signal conditions or component values which shall be supplied by the circuit in which this device is used in order

for it to produce the specified DC and AC electrical output characteristics.

Note 10: Functional and certain other parametric tests utilize a CLC030 as the input source to the SDI inputs of the CLC031. The CLC030 is DC coupled to the

Test Loads

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