CDB5345

DS658DB1

3

LIST OF FIGURES

Figure 1. CDB5345 Controls Tab.................................................................................................... 7

Figure 2. Register Maps Tab........................................................................................................... 8

Figure 3. Block Diagram................................................................................................................ 15

Figure 4. CS5345 .......................................................................................................................... 16

Figure 5. Analog Inputs ................................................................................................................. 17

Figure 6. Analog Outputs .............................................................................................................. 18

Figure 7. S/PDIF Output................................................................................................................ 19

Figure 8. Control Port.................................................................................................................... 20

Figure 9. FPGA ............................................................................................................................. 21

Figure 10. Discrete Clock Routing and Level Shifting................................................................... 22

Figure 11. Power........................................................................................................................... 23

Figure 12. Silk Screen................................................................................................................... 24

Figure 13. Topside Layer .............................................................................................................. 25

Figure 14. Bottom side Layer ........................................................................................................ 26

LIST OF TABLES

Table 1. MCLK Source.................................................................................................................. 11

Table 2. Subclock Source ............................................................................................................. 12

Table 3. CS8406 SDIN Source .....................................................................................................12

Table 4. System Connections ....................................................................................................... 13

Table 5. System Jumper Settings .................................................................................................14

Table 6. Revision History .............................................................................................................. 27