NT5SV64M4AT datasheet(39/65 Pages) ETC1

39 / 65 page

NT5SV64M4AT(L)

NT5SV32M8AT(L)

NT5SV16M16AT(L)

256Mb Synchronous DRAM

REV 1.0

May, 2001

NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.

Read Cycle

Symbol

Parameter

-7K

-75B

-8B

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

tOH

Data Out Hold Time

—

2.5

—

2.7

—

2.7

—

2, 4

tLZ

Data Out to Low Impedance Time

—

tHZ3

Data Out to High Impedance Time

5.4

tHZ2

Data Out to High Impedance Time

5.4

tDQZ

DQM Data Out Disable Latency

—

1. AC Output Load Circuit A.

2. AC Output Load Circuit B.

3. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.

4. Data Out Hold Time with no load must meet 1.8ns (-75H, -75D, -75A).

Refresh Cycle

Symbol

Parameter

-7K

-75B

-8B

Units

Notes

Min.

Max.

Min.

Max.

Min.

Max.

tREF

Refresh Period

—

tSREX

Self Refresh Exit Time

—

1. 8192 a uto refresh cycles.

Write Cycle

Symbol

Parameter

-7K

-75B

-8B

Units

Min.

Max.

Min.

Max.

Min.

Max.

tDS

Data In Set-up Time

1.5

—

1.5

—

tDH

Data In Hold Time

0.8

—

0.8

—

tDPL

Data input to Precharge

—

tDAL3

Data In to Active Delay

CAS Latency = 3

—

tDAL2

Data In to Active Delay

CAS Latency = 2

—

tDQW

DQM Write Mask Latency

—

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