NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

Tables

Tab. 1.

Ordering information ..........................................2

Tab. 2.

Ordering options ................................................3

Tab. 3.

Pin description ...................................................5

Tab. 4.

Register summary ............................................. 6

Tab. 5.

Register 0 - Input port register (address

00h) bit description ............................................7

Tab. 6.

Register 1 - Polarity inversion register

(address 01h) bit description .............................8

Tab. 7.

Register 2 - Bus-hold/pull-up/pull-down

enable register (address 02h) bit

description ......................................................... 8

Tab. 8.

Register 3 - Pull-up/pull-down selector

register (address 03h) bit description ................9

Tab. 9.

Register 4 - Configuration register (address

04h) bit description ............................................9

Tab. 10. Register 5 - Output port register (address

05h) bit description ..........................................10

Tab. 11. Register 6 - Interrupt mask register

(address 06h) bit description ...........................10

Tab. 12. Register 7 - Interrupt status register

(address 07h) bit description ...........................10

Tab. 13. Limiting values ................................................ 16

Tab. 14. Static characteristics ....................................... 16

Tab. 15. Dynamic characteristics .................................. 17

Tab. 16. SnPb eutectic process (from J-STD-020D) ..... 23

Tab. 17. Lead-free process (from J-STD-020D) ............23

Tab. 18. Abbreviations ...................................................24

Tab. 19. Revision history ...............................................25

Figures

Fig. 1.

Block diagram of PCA9574 ...............................3

Fig. 2.

Simplified schematic of the I/Os (P0 to P7) ....... 4

Fig. 3.

Pin configuration for TSSOP16 ......................... 5

Fig. 4.

Pin configuration for HVQFN16 .........................5

Fig. 5.

PCA9574 device address ..................................6

Fig. 6.

Command register .............................................6

Fig. 7.

Bit transfer .......................................................12

Fig. 8.

Definition of START and STOP conditions ...... 12

Fig. 9.

System configuration .......................................13

Fig. 10.

Acknowledgement on the I2C-bus .................. 13

Fig. 11.

Write to Output port register ............................14

Fig. 12.

Write to Polarity inversion, Bus-

hold enable, Pull-up/pull-down selector,

Configuration, Interrupt mask and Interrupt

status registers ................................................14

Fig. 13.

Read from register .......................................... 14

Fig. 14.

Read Input port register .................................. 15

Fig. 15.

Typical application ...........................................15

Fig. 16.

VOH at VDD = 3.3 V, VDD(IO) = 1.2 V, IOH

= -1 mA ...........................................................17

Fig. 17.

VOH at VDD = 3.3 V, VDD(IO) = 3.3 V, IOH

= -1 mA ...........................................................17

Fig. 18.

Definition of timing .......................................... 19

Fig. 19.

Reset timing .................................................... 19

Fig. 20.

Test circuitry for switching times ......................19

Fig. 21.

Package outline SOT403-1 (TSSOP16) ..........20

Fig. 22.

Package outline SOT758-1 (HVQFN16) ......... 21

Fig. 23.

Temperature profiles for large and small

components .....................................................24

PCA9574

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Product data sheet

Rev. 6.0 — 31 May 2023

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