NXP Semiconductors

PCA9574

8-bit I2C-bus and SMBus, level translating, low voltage GPIO with reset and interrupt

6 Pinning information

6.1 Pinning

PCA9574PW

002aad052

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

INT

VDD

A0

SDA

RESET

SCL

P0

P7

P1

P6

P2

P5

P3

P4

VSS

VDD(IO)

Figure 3. Pin configuration for TSSOP16

002aad053

PCA9574BS

Transparent top view

P2

P5

P1

P6

P0

P7

RESET

SCL

4

9

3

10

2

11

1

12

terminal 1

index area

Figure 4. Pin configuration for HVQFN16

6.2 Pin description

Pin

Symbol

TSSOP16

HVQFN16

Type

Description

INT

1

15

O

active LOW interrupt output;

active LOW SMBus alert output

A0

2

16

I

address input

RESET

3

1

I

active LOW reset input

P0

4

2

I/O

input/output 0

P1

5

3

I/O

input/output 1

P2

6

4

I/O

input/output 2

P3

7

5

I/O

input/output 3

VSS

8

6[1]

ground

supply ground

VDD(IO)

9

7

power supply

I/O bank supply voltage

P4

10

8

I/O

input/output 4

P5

11

9

I/O

input/output 5

P6

12

10

I/O

input/output 6

P7

13

11

I/O

input/output 7

SCL

14

12

I

serial clock line

SDA

15

13

I/O

serial data line

VDD

16

14

power supply

supply voltage

Table 3. Pin description

[1]

HVQFN16 package die supply ground is connected to both VSS pin and exposed center pad. VSS pin must be connected to supply ground for

proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a

PCA9574

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© 2023 NXP B.V. All rights reserved.

Product data sheet

Rev. 6.0 — 31 May 2023

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