Nexperia

74LVC163

Presettable synchronous 4-bit binary counter; synchronous reset

10.1. Waveforms and test circuit

mgu762

CP input

Qn, TC output

tPHL

tPLH

tW

VM

VOH

VI

GND

VOL

VM

1/fmax

VM

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 9. Clock (CP) to outputs (Qn, TC) propagation delays, the clock pulse width, and the maximum frequency

mgu763

CET input

TC output

tPLH

tPHL

GND

VI

VM

VM

VM

VM

VOH

VOL

Measurement points are given in Table 8.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 10. Input (CET) to output (TC) propagation delays

mgu764

th

tsu

th

tsu

VM

VM

VM

VI

GND

VI

GND

CP input

MR input

Measurement points are given in Table 8.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 11. The master reset (MR) set-up and hold times

74LVC163

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Product data sheet

Rev. 7 — 19 April 2021

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