Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
99
10.4.12
Local Bus DMA Write; Slow Mode
Operating Conditions: VDDC: 2.2-2.6V, VDDIO: 3.2-3.5V, TA = 0°C to 70°C, Output Load = 25pF
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
T20
Write enable true to DREQ false (2)
17
50
60
ns
T21
Write enable false to DREQ true
23
50
72
ns
T25
DREQ false to DREQ true
15
25
ns
T26
Write enable width (1)
5
ns
T27
Data setup to end of write enable
5
ns
T28
Data hold time from end of write enable
0
ns
T29
Width of EOT# pulse (3)
5
ns
(1) For non-split DMA mode, write enable is the occurrence of DACK# and optionally, IOW#. For split DMA
mode, write enable is the occurrence of DACK# and optionally, DMAWR#.
(2) The minimum value is only guaranteed if the DMA Request Enable bit in the DMAREQ register is set.
(3) EOT#, DACK#, and optionally, IOW# or DMAWR# must all be true for at least T29 for proper recognition of
the EOT# pulse.
T20
T25
T21
T20
T27
T26
T27
T26
T28
T28
T29
D0
D1
0ns
50ns
100ns
150ns
200ns
DREQ
DACK#
IOW# (Optional)
LD[15:0]
EOT# (Optional)
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