Specification
NET2272 USB Peripheral Controller
______________________________________________________________________________
NetChip Technology, Inc., 2003
Patent Pending
335 Pioneer Way, Mountain View, California 94041
TEL (650) 526-1490
FAX (650) 526-1494
http://www.netchip.com
Rev 1.2, October 15, 2003
68
8.6
Endpoint Registers
There are 4 sets of endpoint registers, one for each endpoint. To access an endpoint, set the Page Select field of the
PAGESEL register to the desired endpoint, then read or write to an endpoint register as defined below. Status bits
associated with an endpoint packet buffer (Buffer Full, Buffer Empty, etc), are only valid for the currently visible
buffer. The currently visible buffer is the one that is currently being written to or read from by the local bus.
8.6.1 (Address 05h; EP_DATA) Endpoint Data
Note: If DMA Request is enabled, then this register accesses the endpoint buffer selected by DMA Endpoint Select,
rather than Page Select.
Bits
Description
Read
Write
Default
Value
15:8
Endpoint Data (High Order byte).
When operating with a bus width of 16 bits,
bits [15:8] of this register provide the high order byte.
Yes
Yes
0
7:0
Endpoint Data (Low Order byte). When operating with a bus width of 8 bits, bits
[7:0] of this register provide the data for the buffer transaction (read or write). When
operating with a bus width of 16 bits, bits [7:0] of this register provide the low order
byte.
Yes
Yes
0
8.6.2 (Address 06h; EP_STAT0) Endpoint Status Register (low byte)
Note 1: If DMA Request is enabled, then the Buffer Full and Buffer Empty bits correspond to the endpoint buffer
selected by DMA Endpoint Select, rather than Page Select.
Note 2: The Buffer Full and Buffer Empty bits take up to 100 nsec to become valid after an endpoint buffer is written
or read.
Bits
Description
Read
Write
Default
Value
7
Buffer Full.
This bit is set when the endpoint packet buffer is full. For an IN
endpoint, the currently selected buffer has a count of MaxPkt bytes, or no buffer is
available to the local side for writing (no space to write). For an OUT endpoint,
there is a buffer available on the local side, and there are MaxPkt bytes available to
read (entire packet is available for reading).
Yes
No
0
6
Buffer Empty. For an IN endpoint, a buffer is available to the local side for writing
up to MaxPkt bytes. This bit is set when the endpoint buffer is empty. For an OUT
endpoint, the currently selected buffer has a count of 0, or no buffer is available on
the local side (nothing to read).
Yes
No
1
5
NAK OUT Packets. This bit is set when a short data packet is received from the host
by this endpoint, and the NAK OUT Packets Mode bit of the EP_RSPSET register is
set. Writing a 1 clears this status bit. If this bit is set and another OUT token is
received, a NAK is returned to the host if another OUT packet is sent to this
endpoint. This bit can also be controlled by the EP_RSPCLR and EP_RSPSET
registers.
Yes
Yes/CLR
0
4
Short Packet Transferred Interrupt. This bit is set when the length of the last
packet was less than the Maximum Packet Size (EP_MAXPKT). Writing a 1 clears
this bit.
Yes
Yes/CLR
0
3
Data Packet Received Interrupt. This bit is set when a data packet is received from
the host by this endpoint. Writing a 1 clears this bit.
Yes
Yes/CLR
0
2
Data Packet Transmitted Interrupt. This bit is set when a data packet is
transmitted from the endpoint to the host. Writing a 1 clears this bit.
Yes
Yes/CLR
0
1
Data OUT Token Interrupt. This bit is set when a Data OUT token has been
received from the host.
This bit is also set by PING tokens (in high-speed
only). Writing a 1 clears this bit.
Yes
Yes/CLR
0
0
Data IN Token Interrupt. This bit is set when a Data IN token has been received
from the host. Writing a 1 clears this bit.
Yes
Yes/CLR
0
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