Since the Address Pointer of the device is shared between the regular EEPROM array and the serial number block, a

dummy write sequence, as part of a random read or sequential read protocol, should be performed to ensure the

Address Pointer is set to a known value. Reading the serial number from a location other than the first address of the

block will not result in a unique serial number.

Additionally, the word address contains a ‘10’ sequence in bit A11 and A10 of the word address, regardless of the

intended address as depicted in Table 6-2. If a word address other than ‘10’ is used, then the device will output

undefined data.

Note:  If the application desires to read the first byte of the serial number, the word address input would need to be

0800h.

When the end of the 128-bit serial number is reached (16 bytes of data), continued reading of the extended memory

region will result in an additional 16 bytes of 00h data. Upon reaching the end of the 32-byte extended memory

region, the data word address will rollover back to the beginning of the 128-bit serial number. The serial number read

operation is terminated when the bus master does not respond with an ACK (it NACKs) during the ninth clock cycle.

After the NACK response, the master may send a Stop condition to complete the protocol, or it can send a Start

condition to begin the next sequence (see Figure 8-4).

Figure 8-4. Serial Number Read

SCL

SDA

Start Condition

by Master

Device Address Byte

First Word Address Byte

MSb

MSb

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

1

A

2

A

1

A

0

0

0

Dummy Write

X

X

X

X

1

0

X

X

0

ACK

from Slave

ACK

from Slave

Second Word Address Byte

MSb

X

ACK

from Slave

X

0

X

0

0

0

0

0

Start Condition

by Master

ACK

from Slave

NACK

from Master

Stop Condition

by Master

ACK

from Master

Device Address Byte

Serial Number Byte0

Serial Number Byte15

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

0

1

1

A

2

A

1

A

0

1

0

D7 D6 D5 D4 D3 D2 D1 D0

0

D7 D6 D5 D4 D3 D2 D1 D0

1

MSb

MSb

MSb

AT24CS32

Read Operations

© 2020 Microchip Technology Inc.

Datasheet

DS20006341A-page 23