UPD75P4308 datasheet(39/61 Pages) RENESAS

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µPD75P4308

Data Sheet U10909EJ2V1DS

High-level output

ILOH1

VO = VDD

SCK, SO/SB0, Ports 2, 3, 6 to 8

µA

leakage current

ILOH2

VO = 13 V

Port 5 (N-ch open-drain)

µA

Low-level output

ILOL

VO = 0 V

–3

µA

leakage current

On-chip pull-up

VI = 0 V

Ports 0 to 3, 6 to 8 (except P00 pin)

100

200

Ω

resistor

Supply currentNote 1

IDD1

VDD = 5.0 V

± 10 %Note 2

2.20

7.00

VDD = 3.0 V

± 10 %Note 3

0.43

1.30

IDD2

HALT

VDD = 5.0 V

± 10 %

0.53

1.60

mode

VDD = 3.0 V

± 10 %

0.21

0.70

IDD1

VDD = 5.0 V

± 10 %Note 2

1.70

5.10

VDD = 3.0 V

± 10 %Note 3

0.35

1.10

IDD2

HALT

VDD = 5.0 V

± 10 %

0.51

1.60

mode

VDD = 3.0 V

± 10 %

0.19

0.60

IDD5

STOP

VDD = 5.0 V

± 10 %

0.05

10.0

µA

mode

VDD = 3.0 V

± 10 %

0.02

5.00

µA

TA = 25˚C

0.02

3.00

µA

Notes 1. The current flowing through the on-chip pull-up resistor is not included.

2. When the device operates in high-speed mode with the processor clock control register (PCC) set to

0011.

3. When the device operates in low-speed mode with PCC set to 0000.

6.0 MHz

crystal

oscillation

C1 = C2

= 22 pF

4.19 MHz

crystal

oscillation

C1 = C2

= 22 pF

DC Characteristics (TA = –40 to +85˚C, VDD = 1.8 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

UPD75P4308 데이터시트(PDF) 39 Page - Renesas Technology Corp

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