UPD9971 datasheet(49/112 Pages) RENESAS

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µPD9971

Data Sheet S17455EJ2V0DS

This block operates according to the STMSI and STMSO register settings. For details, refer Table 5-8.

Table 5-8 Pin Statuses in MSIO Block

MMS = 0 (Slave Mode)

MMS = 1 (Master Mode)

(STMSI, STMSO)

Pin Function

(0, 0)

(1, 1)

(1, 0)

(0, 1)

(0, 0)

(1, 1)

(1, 0)

(0, 1)

MBCLK

Bit synchronization I/O

for PCM sound generator-

core

Input

(Internal:

Low)

Input

Low

Output

MEN

Frame synchronization I/O

for PCM sound generator-

core

Input

(Internal:

Low)

Input

Low

Output

MSI

PCM sound generator-core

serial data input

−

Input

−

Input

−

MSO

PCM sound generator-core

serial data output

Hi-Z

Output

Hi-Z

Output

Hi-Z

Output

Hi-Z

Output

Cautions 1. As in the case of ASIO, MSIO can operate in the slave or master mode.

When ASIO and MSIO are used at the same time, the frame signals in the

µPD9971 need to be

integrated. Accordingly, ASIO can be used in the master mode only.

2. Below are the restrictions that are applied depending on use conditions.

(1)When only ASIO set to the master mode is used, the setting value of BFS must be only

64 fs or 32 fs.

(2)When only MSIO set to the master mode is used, the setting value of MBSF must be

selected from among 32 fs, 64 fs, 128 fs, and 256 fs.

(3)When both ASIO and MSIO are used, ASIO can be used only if it is set to the master

mode.

(4)In all of the above cases, the setting of invalid values to BFS or MBFS results in the

application of default values.

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