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UPD9971 데이터시트(PDF) 80 Page - Renesas Technology Corp

부품명 UPD9971
상세설명  MOS INTEGRATED CIRCUIT
PDF  112 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

UPD9971 데이터시트(HTML) 80 Page - Renesas Technology Corp

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µPD9971
Data Sheet S17455EJ2V0DS
78
8.2.3 FS switching
Step
Item
Target registers, pins, etc.
1
Switching to Control register bank (when the PS
pin = 1)
BANK
2
Setting of digital volume mute
MELLDG, MELRDG, AULDG, AURDG
3
Setting of analog volume mute
ADACLVRGA, ADACRVRGA
4
Setting of standby state
STPLL1, STPLL2, STREF, STSYNTH, …
5
Setting of sampling frequency
FS, BFS
6
Setting of MSIO mode
MBFS, MMS, SMEN, SMBCLK, MCHI, MCHO
7
Canceling VREF standby
STREF
8
Canceling PLL standby
STPLL1 and STPLL2 (5 ms after the STREF standby is canceled)
9
Canceling function block standby
STSYNTH, STADIG, STADAC, …
10
The internal clock is valid.
5 ms after the STPLL1 and STPLL2 standby is canceled
11
Canceling analog volume mute
ADACLVRGA, ADACRVRGA
12
Canceling digital volume mute
MELLDG, MELRDG, AULDG, AURDG
8.2.4 Path switching
Step
Item
Target registers, pins, etc.
1
Switching to Control register bank (when the PS
pin = 1)
BANK
2
Setting of digital volume mute
MELLDG, MELRDG, AULDG, AURDG
3
Setting of analog volume mute
ADACLVRGA, ADACRVRGA
4
Setting of standby state
STPLL1, STPLL2, STREF, STSYNTH, …
5
Setting of path (digital mixing)
DACLSW, DACRSW, DACLMIX, DACRMIX,
MELLSW, MELRSW, MELLMIX, MELRMIX
6
Canceling VREF standby
STREF
7
Canceling PLL standby
STPLL1 and STPLL2 (5 ms after STREF standby is canceled)
8
Canceling function block standby
STSYNTH, STADIG, STADAC, …
9
The internal clock is valid.
5 ms after STPLL1 and STPLL2 standby is canceled
10
Canceling analog volume mute
ADACLVRGA, ADACRVRGA
11
Canceling digital volume mute
MELLDG, MELRDG, AULDG, AURDG



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