전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

DIX4192IPFBT 데이터시트(PDF) 18 Page - Burr-Brown (TI)

[Old version datasheet] Texas Instruments acquired Burr-Brown Corporation.
부품명 DIX4192IPFBT
상세설명  Integrated Digital Audio Interface Receiver and Transmitter
PDF  60 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  BURR-BROWN [Burr-Brown (TI)]
홈페이지  http://www.burr-brown.com
Logo BURR-BROWN - Burr-Brown (TI)

DIX4192IPFBT 데이터시트(HTML) 18 Page - Burr-Brown (TI)

Back Button DIX4192IPFBT Datasheet HTML 14Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 15Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 16Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 17Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 18Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 19Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 20Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 21Page - Burr-Brown (TI) DIX4192IPFBT Datasheet HTML 22Page - Burr-Brown (TI) Next Button
Zoom Inzoom in Zoom Outzoom out
 18 / 60 page
background image
www.ti.com
SY C
N
BLS
(input)
BLS
(output)
Block Start
(Frame 0startshere)
DIGITAL INTERFACE RECEIVER (DIR) OPERATION
PL 1
L
AE 3
S
Decoder
Pulse
Generator
PL 2
L
128f
S
256f
S
512f
S
Clock
Divider
Divide by
1,2, 4,or8
DataStream
De-M x
u
RX1+(pin1)
RX1 (pin2)
-
RX2+(pin3)
RX2 (pin4)
-
RX3+(pin5)
RX3 (pin6)
-
RX4+(pin7)
RX4 (pin8)
-
LOCK
(pin 11)
RXCKO
(pin 12)
RXCKO
BYPMUX[10
: ]
R MUX[
X
1:0]
RXCLK
MC K
L
RXCKI
RXCKOF[1:0]
Ch1
.
(Left)
Audio
Ch2
.
(Right)
Audio
Cha ne
n
l
Status
Channel
Status
User
Daa
t
User
Daa
t
UserAccess
(UA)Buffers
Receiver
Access
(RA)Buffers
To
DIT
ToSPI orI CHostInterface
2
Receiver
Sy c
n
Generator
RCV_SYNC
Errorand
StatusOutputs
ToDIT Buffer
andLine Driver
Reference
Clock
Source
To
DIT
DIX4192
SBFS031C – JANUARY 2006 – REVISED JUNE 2006
PRODUCT OVERVIEW (continued)
Figure 11. DIT Block Start Timing
The DIR performs AES3 decoding and clock recovery and provides the differential line receiver functions. The
lock range of the DIR includes frame/sampling rates from 20kHz to 216kHz. Figure 12 shows the functional
block diagram for the DIR.
Four differential line receivers are utilized for signal conditioning the encoded input data streams. The receivers
can be externally configured for either balanced or unbalanced cable interfaces, as well as interfacing with
CMOS logic level inputs from optical receivers or external logic circuitry. See Figure 13 for a simplified
schematic for the line receiver. External connections are discussed in the Receiver Input Interfacing section.
Figure 12. Digital Interface Receiver (DIR) Functional Block Diagram
18
Submit Documentation Feedback



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com