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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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12F683 데이터시트(PDF) 88 Page - Microchip Technology |
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12F683 데이터시트(HTML) 88 Page - Microchip Technology |
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88 / 148 page  PIC12F683 DS41211B-page 86 Preliminary 2004 Microchip Technology Inc. 12.4.2 TMR0 INTERRUPT An overflow (FFh → 00h) in the TMR0 register will set the T0IF (INTCON<2>) bit. The interrupt can be enabled/disabled by setting/clearing T0IE (INTCON<5>) bit. See Section 5.0 “Timer0 Module” for operation of the Timer0 module. 12.4.3 GPIO INTERRUPT An input change on GPIO change sets the GPIF (INTCON<0>) bit. The interrupt can be enabled/ disabled by setting/clearing the GPIE (INTCON<3>) bit. Plus, individual pins can be configured through the IOC register. FIGURE 12-7: INTERRUPT LOGIC Note: If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set. TMR1IF TMR1IE CMIF CMIE T0IF T0IE INTF INTE GPIF GPIE GIE PEIE Wake-up (If in Sleep mode) Interrupt to CPU EEIE EEIF ADIF ADIE IOC-GP0 IOC0 IOC-GP1 IOC1 IOC-GP2 IOC2 IOC-GP3 IOC3 IOC-GP4 IOC4 IOC-GP5 IOC5 TMR2IF TMR2IE CCP1IF CCP1IE OSFIF OSFIE |
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