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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD78323LP 데이터시트(PDF) 35 Page - Renesas Technology Corp |
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UPD78323LP 데이터시트(HTML) 35 Page - Renesas Technology Corp |
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35 / 88 page  33 µPD78323, 78324 Figure 3-2. Externally-Mounted System Clock Generator (a) Crystal oscillator Cautions 1. When the system clock oscillator is used, the following points should be noted concerning wiring within broken lines shown in Figure 3-2, in order to prevent the effects of wiring capacitance, etc. • Keep the wiring as short as possible. • Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. • Ensure that oscillator capacitor connection points are always at the same potential as VSS. Do not ground in a ground pattern in which a high current flows. • Do not take a signal from the oscillator. 2. When an external clock is input to the X1 pin and the X2 pin is left open, ensure that no loads such as wiring capacitance are connected to the X2 pin. (b) External clock (i) When the inverted phase of an external clock to be input to the X1 pin is input to the X2 pin (ii) When X2 pin is left open X2 X1 VSS PD78324 µ X1 X2 External Clock PD78324 µ X1 X2 Open External Clock PD78324 µ |
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