M24512-W, M24512-R, M24256-BW, M24256-BR

Device operation

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3.9

ECC (Error Correction Code) and Write cycling

The M24512-W, M24512-R, M24256-BW and M24256-BR devices offer an ECC (Error

Correction Code) logic which compares each 4-byte packet with its associated ECC bits (6

EEPROM bits). As a result, if a single bit out of 4 bytes of data happens to be erroneous

during a Read operation, the ECC detects it and replaces it by the correct value. The read

reliability is therefore much improved by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC bits), that is, the addressed Byte is cycled together with the other three bytes

making up the packet. It is therefore recommended to write by packets of 4 bytes in order to

benefit from the larger amount of Write cycles.

The M24512-W, M24512-R, M24256-BW and M24256-BR devices are qualified at 1 million

(1,000,000) Write cycles, using a cycling routine that writes to the device by multiples of 4-

bytes.

Caution:

Note that the M24512-W and M24512-R in SO8 Wide package (MW) are offered with either

the previous die qualified at 100.000 Write cycles or the new die (qualified at 1 Million Write

cycles). The two dice are distinguished by their respective process letter: "V" for the

previous die and " A" for the new die. Please contact your nearest ST sales office for more

information.

Figure 7.

Write Mode sequences with WC = 0 (data write enabled)

BYTE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN

WC

PAGE WRITE

DEV SEL

BYTE ADDR

BYTE ADDR

DATA IN 1

WC

DATA IN 2

AI01106C

PAGE WRITE

(cont'd)

WC (cont'd)

DATA IN N

ACK

R/W

ACK

ACK

ACK

ACK

ACK

ACK

ACK

R/W

ACK

ACK