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M24512-WDW6TP 데이터시트(PDF) 22 Page - STMicroelectronics |
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M24512-WDW6TP 데이터시트(HTML) 22 Page - STMicroelectronics |
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22 / 31 page ![]() DC and AC parameters M24512-W, M24512-R, M24256-BW, M24256-BR 22/31 Table 12. DC characteristics (M24xxx-R) Symbol Parameter Test conditions (see Table 8 and Table 9) Min. Max. Unit ILI Input Leakage Current (SCL, SDA, E2, E1, E0) VIN = VSS or VCC device in Stand-by mode ± 2 µA ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ± 2 µA ICC Supply Current (Read) VCC =1.8V, fc = 400kHz (rise/fall time < 30ns) 1mA ICC0 Supply Current (Write) During tW, 1.8V < VCC < 5.5V 5(1) 1. Characterized value, not tested in production. mA ICC1 Standby Supply Current VIN = VSS or VCC, VCC = 1.8 V 2 µA VIL Input Low Voltage –0.45 0.3 VCC V VIH Input High Voltage 0.7VCC VCC+1 V VOL Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V 0.2 V Table 13. AC characteristics (M24xxx-W, see Table 7 and Table 9) Symbol Alt. Parameter Min. Max. Unit fC fSCL Clock Frequency 400 kHz tCHCL tHIGH Clock Pulse Width High 600 ns tCLCH tLOW Clock Pulse Width Low 1300 ns tCH1CH2 tR Clock Rise Time 300 ns tCL1CL2 tF Clock Fall Time 300 ns tDH1DH2 (1) 1. Sampled only, not 100% tested. tR SDA Rise Time 20 300 ns tDL1DL2 (1) tF SDA Fall Time 20 300 ns tDXCX tSU:DAT Data In Set Up Time 100 ns tCLDX tHD:DAT Data In Hold Time 0 ns tCLQX tDH Data Out Hold Time 200 ns tCLQV (2) 2. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA. tAA Clock Low to Next Data Valid (Access Time) 200 900 ns tCHDX (3) 3. For a reSTART condition, or following a Write cycle. tSU:STA Start Condition Set Up Time 600 ns tDLCL tHD:STA Start Condition Hold Time 600 ns tCHDH tSU:STO Stop Condition Set Up Time 600 ns tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns tW tWR Write Time 5 ms |
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