WM8721 / WM8721L

Production Data

w

PD Rev 4.0 November 2004

20

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

1:0

FORMAT[1:0]

10

Audio Data Format Select

11 = DSP Mode, frame sync +

2 data packed words

10 = I

left-1 justified

01 = MSB-First, left justified

00 = MSB-First, right justified

3:2

IWL[1:0]

10

Input Audio Data Bit Length

Select

11 = 32 bits

10 = 24 bits

01 = 20 bits

00 = 16 bits

0000111

Digital Audio

Interface

Format

4

LRP

0

DACLRC phase control (in left,

right or I

1 = Right Channel DAC data

when DACLRC high

0 = Right Channel DAC data

when DACLRC low

(opposite phasing in I

or

DSP mode A/B select ( in DSP

mode only)

1 = MSB is available on 2

nd

BCLK rising edge after

DACLRC rising edge

0 = MSB is available on 1st

BCLK rising edge after

DACLRC rising edge

5

LRSWAP

0

DAC Left Right Clock Swap

1 = Right Channel DAC Data

Left

0 = Right Channel DAC Data

Right

6

MS

0

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

7

BCLKINV

0

Bit Clock Invert

1 = Invert BCLK

0 = Don’t invert BCLK

Table 7 Digital Audio Interface Control

Note: If right justified 32 bit mode is selected then the WM8721 defaults to 24 bits.

MASTER AND SLAVE MODE OPERATION

The WM8721 can be configured as either a master or slave mode device. As a master mode device

the WM8721 controls sequencing of the data and clocks on the digital audio interface. As a slave

device the WM8721 responds with data to the clocks it receives over the digital audio interface. The

mode is set with the MS bit of the control register as shown in Table 8.

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000111

Digital Audio Interface

Format

6

MS

0

Master Slave Mode Control

1 = Enable Master Mode

0 = Enable Slave Mode

Table 8 Programming Master/Slave Modes