Production Data

WM8721 / WM8721L

w

PD Rev 4.0 November 2004

21

As a master mode device the WM8721 controls the sequencing of data transfer (DACDAT) and

output of clocks (BCLK, DACLRC) over the digital audio interface. It uses the timing generated from

the MCLK input as the reference for the clock and data transitions. This is illustrated in Figure 16.

DACDAT is always an input to the WM8721 independent of master or slave mode.

BCLK

DACDAT

DACLRC

WM8721

DAC

DSP

DECODER

Figure 16 Master Mode

As a slave device the WM8721 sequences the data transfer (DACDAT) over the digital audio

interface in response to the external applied clocks (BCLK, DACLRC). This is illustrated in Figure 17.

BCLK

DACDAT

DACLRC

WM8721

DAC

DSP

DECODER

Figure 17 Slave Mode

Note that the WM8721 relies on controlled phase relationships between audio interface BCLK,

DACLRC and the master MCLK. To avoid any timing hazards, refer to the timing section for detailed

information.

AUDIO DATA SAMPLING RATES

The WM8721 provides for two modes of operation (normal and USB) to generate the required DAC

sampling rates. Normal and USB modes are programmed under software control according to the

table below.

In Normal mode, the user controls the sample rate by using an appropriate MCLK frequency and the

sample rate control register setting. The WM8721 can support sample rates from 8ks/s up to 96ks/s.

In USB mode, the user must use a fixed MLCK frequency of 12MHz to generate sample rates from

8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus) clock is at

12MHz and the WM8721 can be directly used within such systems. WM8721 can generate all the

normal audio sample rates from this one Master Clock frequency, removing the need for different

master clocks or PLL circuits.