M58LR128HT datasheet(16/112 Pages) STMICROELECTRONICS

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Bus operations

M58LR128HT, M58LR128HB

16/112

3.5

Standby

Standby disables most of the internal circuitry allowing a substantial reduction of the current

consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power

consumption is reduced to the standby level IDD3 and the outputs are set to high impedance,

independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH

during a program or erase operation, the device enters Standby mode when finished.

3.6

Reset

During Reset mode the memory is deselected and the outputs are high impedance. The

memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the

Reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If

Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory

content is no longer valid.

Table 3.

Bus operations(1)

X = Don't care.

Operation

WAIT(2)

WAIT signal polarity is configured using the Set Configuration Register command.

DQ15-DQ0

Bus Read

VIL

VIH

VIL

(3)

L can be tied to VIH if the valid address has been previously latched.

VIH

Data Output

Bus Write

VIL

VIH

VIL

(3)

VIH

Data Input

Address Latch

VIL

XVIH

VIL

VIH

Data Output or Hi-Z(4)

Depends on G.

Output Disable

VIL

VIH

XVIH

Hi-Z

Standby

VIH

Hi-Z

Reset

XXX

VIL

Hi-Z

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