M58LR128HB datasheet(13/112 Pages) STMICROELECTRONICS

13 / 112 page

M58LR128HT, M58LR128HB

Signal descriptions

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2.7

Reset (RP)

The Reset input provides a hardware reset of the memory. When Reset is at VIL, the

memory is in reset mode: the outputs are high impedance and the current consumption is

reduced to the Reset Supply Current IDD2. Refer to Table 21: DC characteristics - currents,

for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration

mode the device enters asynchronous read mode, but a negative transition of Chip Enable

or Latch Enable is required to ensure valid data outputs.

The Reset pin can be interfaced with 3 V logic without any additional circuitry. It can be tied

to VRPH (refer to Table 22: DC characteristics - voltages).

2.8

Latch Enable (L)

Latch Enable latches the address bits on its rising edge. The address latch is transparent

when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH.

2.9

Clock (K)

The clock input synchronizes the memory to the microcontroller during synchronous read

operations; the address is latched on a Clock edge (rising or falling, according to the

configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous

read and in write operations.

2.10

Wait (WAIT)

Wait is an output signal used during synchronous read to indicate whether the data on the

output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is

at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance.

The WAIT signal is high impedance when Output Enable is at VIH.

2.11

VDD supply voltage

VDD provides the power supply to the internal core of the memory device. It is the main

power supply for all operations (Read, Program and Erase).

2.12

VDDQ supply voltage

VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered

independently from VDD. VDDQ can be tied to VDD or can use a separate supply.

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