CS51031GD8G datasheet(4/10 Pages) ONSEMI

4 / 10 page

CS51031

http://onsemi.com

VGATE

PGND

VGATE

Flip−Flop

−

VFB

Comparator

VFB

1.25 V

0.7 V

Hold Off

Comp

Fault

Comp

1.15 V

CS Charge

Sense

Comparator

Slow Discharge

Flip−Flop

GND

−

Slow Discharge

Comparator

2.3 V

2.4 V

−

Comparator

2.5 V

1.5 V

VREF = 3.3 V

COSC

2.5 V

1.5 V

VREF

3.3 V

VCCOK

VCC

Oscillator

Comparator

VCC

VREF

7IC

Figure 2. Block Diagram

CIRCUIT DESCRIPTION

THEORY OF OPERATION

Control Scheme

The CS51031 monitors the output voltage to determine

when to turn on the P−Ch FET. If VFB falls below the internal

reference voltage of 1.25 V during the oscillator’s charge

cycle, the P−Ch FET is turned on and remains on for the

duration of the charge time. The P−Ch FET gets turned off

and remains off during the oscillator’s discharge time with

the maximum duty cycle to 80%. It requires 7.0 mV typical,

and 20 mV maximum ripple on the VFB pin is required to

operate. This method of control does not require any loop

stability compensation.

CS51031GD8G 데이터시트(PDF) 4 Page - ON Semiconductor

CS51031GD8G 데이터시트(HTML) 4 Page - ON Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10

데이터시트 다운로드

링크 URL