NB650/NB650H

– 6A, 28V, FAST-TRANSIENT, SYNCHRONOUS STEP-DOWN CONVERTERS

NB650/NB650H Rev. 1.13

www.MonolithicPower.com

11

10/7/2019

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

Preliminary Specifications Subject to Change

© 2019 MPS. All Rights Reserved.

R1

R2

ESR

POSCAP

SW

FB

Vo

L

Figure 7: Simplified Circuit in PWM Mode without

External Ramp Compensation

To realize the stability without the use of an

external ramp, select an ESR value as follows:

SW

ON

ESR

OUT

tt

0.7

2

R

C







(4)

Where tSW is the switching period.

Ramp with Small ESR Capacitor

The ESR ripple when using ceramic output

capacitors is not high enough to stabilize the

system and requires an external compensation

ramp.

The

application

section

includes

a

description

of

designing

with

small

ESR

capacitors.

R1

R2

Ceramic

SW

FB

Vo

L

R4

C4

IR4

IC4

IFB

R9

Figure 8: Simplified Circuit in PWM Mode with

External Ramp Compensation

Figure 7 shows a simplified equivalent circuit in

PWM mode with the HS-FET OFF and an

external ramp compensation circuit (R4, C4). The

external ramp is derived from the inductor ripple

current. If one chooses C4, R9, R1 and R2 to

meet the following condition:

12

9

SW

4

1

2

RR

11

R

2

f

C

5

R

R





 













(5)

Where:

R4

C4

FB

C4

I

I

I

I







(6)

And R2 is the equivalent resistor from FB to GND

that varies with VID input, the ramp on the VFB

can then be estimated as:

IN

O

12

RAMP

ON

4

4

1

2

9

VV

R // R

Vt

R

C

R // R

R











(7)

Usually R9 is set to 0

Ω, then equation 7 can be

simplified as:

4

4 C

R

)

V

V

(

V

ON

O

IN

RAMP











(8)

The downward slope of the VFB ripple then

follows

OUT

RAMP

SLOPE1

off

4

4

V

V

V

t

R

C









(9)

As shown in equation 8, if there is instability in

PWM mode, we can reduce either R4 or C4. If

C4 can not be reduced further due to limitations

from equation 5, then we can only reduce R4.

For a stable PWM operation, the Vslope1 should be

designed as follows.

3

10

SW

ON

ESR

OUT

slope1

OUT

OUT

SW

on

tt

+

-R

C

Io

0.7

π

2

-V

V

+

2 L C

t

-t











(10)

Where IO is the load current.

In skip mode, the downward slope of the VFB

ripple is almost the same with or without the

external ramp. Figure 9 shows the simplified

circuit of the skip mode when both HS-FET and

LS-FET are off.

R1

R2

Cout

FB

Vo

Ro

Figure 9: Simplified Circuit in Skip Mode

The downward slope of the VFB ripple in skip

mode can be determined as:





REF

SLOPE2

1

2

OUT

V

V

( R

R

// Ro) C







(11)