January 16, 2020

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ES9028Q2M Datasheet

5

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

FUNCTIONAL DESCRIPTION

NOTATATIONS for Sampling Rates

Mode

fs (target sample rate)

FSR (raw sample rate)

DSD

DATA_CLK / 64

DSD data rate

Serial (PCM) Normal Mode

Frame Clock Rate

Frame Clock Rate

Serial (PCM) OSF Bypass Mode

Frame Clock Rate / 8

Frame Clock Rate

SPDIF

SPDIF Sampling Rate

SPDIF Sampling Rate

PCM, SPDIF and DSD Pin Connections

PCM Audio Format

Notes:

XI clock (MCLK) must be > 192 x FSR when using PCM input (normal mode), or 128 x FSR (synchronous MCLK).

XI clock (MCLK) must be > 24 x FSR when using PCM input (OSF bypass mode).

Pin Name

Description

DATA1

Frame clock

DATA2

2-channel PCM serial data

DATA_CLK

Bit clock for PCM audio format

Master Mode (32-bit data only)

W

hen Register #1 ‘input_select’ is set to 2’d0 (I2S) and ‘i2s_length’ is set to 2’d2 (32-bit), the DAC can become a

master for Bit Clock and Frame Clock by setting Register #10

‘master clock enable’ to 1’b1. The Bit Clock frequency

can be configured to MCLK / 4, MCLK / 8 or MCLK / 16 by setting Register #10

‘clock divider select’ to 2’b00, 2’b01

or 2’b10. GPIO 1 (or 2) can be configured to output MCLK by setting Register #8 gpio1_cfg (or gpio2_cfg) to 4’d3.