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January 16, 2020

ES9028Q2M Datasheet

ESS TECHNOLOGY, INC. 109 Bonaventura Dr., San Jose, CA 95134, USA. Tel (408) 643-

8800 • WWW.ESSTECH.COM

6

SPDIF Audio Formant

Note: XI clock (MCLK) must be > 386 x FSR when using the SPDIF input.

Up to three SPDIF inputs can be connected to the 3-to-

1 mux, selectable via register “spdif_sel”. The SPDIF can also be

sourced from GPIO pins configured as inputs.

Pin Name

Description

GPIO2

SPDIF input 5

GPIO1

SPDIF input 4

DATA1

SPDIF input 3

DATA2

SPDIF input 2

DATA_CLK

SPDIF input 1

DSD Audio Format

Note: XI clock (MCLK) must be > 3 x FSR when using the DSD input.

Pin Name

Description

DATA[1:2]

2-channel DSD data input

DATA_CLK

Bit clock for DSD data input

The MCLK will run at 100MHz which means that the maximum DSD clock frequency supported is 33.3MHz. Hence, octuple-

rate DSD or DSD-22.6MHz is supported by the ES9028Q2M. Note that it is essential to meet the requirement of MCLK > 3 x

DSD_CLK or the circuit will not function correctly.