Philips Semiconductors

Product specification

Silicon Diffused Power Transistor

BUT12AI

Fig.3. Test circuit resistive load. VIM = -6 to +8 V

V

R

Fig.4. Switching times waveforms with resistive load.

Fig.5. Test circuit inductive load.

V

Fig.6. Switching times waveforms with inductive load.

Fig.7. Test circuit RBSOA. V

L

Fig.8. Normalised power dissipation.

PD% = 100

⋅PD/PD

tp

T

VCC

R

R

T.U.T.

0

VIM

B

L

IC

IB

ICon

IBon

-IBoff

t

t

ts

tf

toff

10 %

90 %

IC

IB

10 %

10 %

90 %

90 %

ton

toff

ts

tf

IBon

-IBoff

ICon

tr

30ns

LB

IBend

-VBB

LC

T.U.T.

VCC

VCL

CFB

LB

IBon

-VBB

LC

T.U.T.

VCC

0

20

40

60

80

100

120

140

Tmb / C

PD%

Normalised Power Derating

120

110

100

90

80

70

60

50

40

30

20

10

0

June 1997

3

Rev 1.000