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CC2500-RTR1 데이터시트(PDF) 20 Page - Texas Instruments

부품명 CC2500-RTR1
상세설명  Single Chip Low Cost Low Power RF Transceiver
PDF  84 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI - Texas Instruments

CC2500-RTR1 데이터시트(HTML) 20 Page - Texas Instruments

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CC2500
PRELIMINARY Data Sheet (Rev.1.2)
SWRS040A
Page 20 of 83
0
A6
A5
A4
A3
A2
A0
A1
D
W
7
D
W
6
D
W
5
D
W
4
D
W
3
D
W
2
D
W
1
D
W
0
1
A6
A5
A4
A3
A2
A0
A1
D
R
7
D
R
6
D
R
5
D
R
4
D
R
3
D
R
2
D
R
1
D
R
0
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO
Hi-Z
t
sp
t
ch
t
cl
t
sd
t
hd
t
ns
X
X
Hi-Z
X
S7
S6
S5
S4
S3
S2
S1
S0
Hi-Z
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
S7
X
Figure 7: Configuration register write and read operations (A6 is the “burst” bit)
Parameter
Description
Min
Max
Units
SCLK
frequency
100 ns delay inserted between address byte and data byte (single access), or between
address and data, and between each data byte (burst access).
-
10
MHz
SCLK
frequency, single access
No delay between address and data byte
9
MHz
fSCLK
SCLK
frequency, burst access
No delay between address and data byte, or between data bytes
6.5
MHz
tsp,pd
CSn
low to positive edge on SCLK, in power-down mode
200
-
µs
tsp
CSn
low to positive edge on SCLK, in active mode
20
-
ns
tch
Clock high
50
-
ns
tcl
Clock low
50
-
ns
trise
Clock rise time
-
5
ns
tfall
Clock fall time
-
5
ns
Single access
55
-
ns
tsd
Setup data (negative SCLK edge) to
positive edge on SCLK
(tsd applies between address and data bytes, and
between data bytes)
Burst access
76
-
ns
thd
Hold data after positive edge on SCLK
20
-
ns
tns
Negative edge on SCLK to CSn high
20
-
ns
Table 16: SPI interface timing requirements
DATA
byte 0
ADDR
FIFO
DATA
byte 1 DATAbyte 2
DATA
byte n-1 DATAbyte n
...
ADDR
strobe
DATA
ADDR
strobe
ADDRreg
ADDRreg n
DATAn
DATAn+1
DATAn+2
...
ADDR
strobe
...
CSn:
Command strobe(s):
Read or write register(s):
Read or write consecutive registers (burst):
DATA
ADDRreg
DATA
ADDRreg
...
DATA
byte 0
ADDR
FIFO
DATA
byte 1
Combinations:
DATA
ADDR
reg
DATA
ADDR
reg
ADDR
strobe
ADDR
strobe
...
Read or write n+1 bytes from/to RF FIFO:
Figure 8: Register access types



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