Production Data

WM8569

w

PD Rev 4.0 June 2006

15

System Clock Frequency (MHz)

128fs

192fs

SAMPLING

RATE

(DACLRC/

ADCLRC)

DAC only

DAC only

256fs

384fs

512fs

768fs

32kHz

4.096

6.144

8.192

12.288

16.384

24.576

44.1kHz

5.6448

8.467

11.2896

16.9340

22.5792

33.8688

48kHz

6.144

9.216

12.288

18.432

24.576

36.864

96kHz

12.288

18.432

24.576

36.864

Unavailable Unavailable

192kHz

24.576

36.864

Unavailable Unavailable Unavailable Unavailable

Table 6 System Clock Frequencies Versus Sampling Rate

HARDWARE CONTROL MODES

When the MODE pin is held high, the following hardware modes of operation are available.

Note: When in hardware mode the ADC and DAC will only run in slave mode.

MUTE AND AUTOMUTE OPERATION

In both hardware and software modes, MUTE controls the selection of MUTE directly, and can be

used to enable and disable the automute function. This pin becomes an output when left floating and

indicates infinite ZERO detect (IZD) has been detected.

DESCRIPTION

0

Normal Operation

1

Mute DAC channels

Floating

Enable IZD, MUTE becomes an output to indicate when IZD occurs.

L=IZD detected, H=IZD not detected.

Table 7 Mute and Automute Control

Figure 9 shows the application and release of MUTE whilst a full amplitude sinusoid is being played

at 48kHz sampling rate. When MUTE (lower trace) is asserted, the output (upper trace) begins to

with a time constant of approximately 64 input samples. If MUTE is applied to all channels for 1024

asserted, the output will restart immediately from the current input sample.

Figure 9 Application and Release of Soft Mute

-2.5

-2

-1.5

-1

-0.5

0

0.5

1

1.5

0

0.001

0.002

0.003

0.004

0.005

0.006

Time(s)