Production Data

WM8569

w

PD Rev 4.0 June 2006

23

CONTROL INTERFACE REGISTERS

ATTENUATOR CONTROL MODE

Setting the ATC register bit causes the left channel attenuation settings to be applied to both the left

and right channel of the DAC from the next audio input sample. No update to the attenuation

registers is required for ATC to take effect.

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

3

ATC

0

Attenuator Control Mode:

0: Right channel use right

attenuations

1: Right channel use left

attenuations

INFINITE ZERO DETECT ENABLE

Setting the IZD register bit will enable the internal infinite zero detect function:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0000010

DAC Channel Control

4

IZD

0

Infinite Zero Mute Enable

0 : Disable inifinite zero mute

1: Enable infinite zero mute

With IZD enabled, applying 1024 consecutive zero input samples each stereo channel will cause that

receives a non-zero input.

DAC OUTPUT CONTROL

The DAC output control word determines how the left and right input to the audio Interface are

applied to the left and right DAC:

REGISTER ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

PL[3:0]

Left

Output

Right

Output

0000

Mute

Mute

0001

Left

Mute

0010

Right

Mute

0011

(L+R)/2

Mute

0100

Mute

Left

0101

Left

Left

0110

Right

Left

0111

(L+R)/2

Left

1000

Mute

Right

1001

Left

Right

1010

Right

Right

1011

(L+R)/2

Right

1100

Mute

(L+R)/2

1101

Left

(L+R)/2

1110

Right

(L+R)/2

0000010

DAC Control

8:5

PL[3:0]

1001

1111

(L+R)/2

(L+R)/2