WM8772SEDSSLASHRV datasheet(53/73 Pages) WOLFSON

53 / 73 page

Production Data

WM8772EFT – 32 LEAD TQFP

PD Rev 4.2 October 2005

LEFT JUSTIFIED MODE

In left justified mode, the MSB of DIN1/2/3 is sampled by the WM8772EFT on the first rising edge of

DACBCLK following a DACLRC transition. The MSB of the ADC data is output on DOUT and

changes on the same falling edge of ADCBCLK as ADCLRC and may be sampled on the rising edge

of ADCBCLK. ADCLRC and DACLRC are high during the left samples and low during the right

samples (Figure 47).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 47 Left Justified Mode Timing Diagram

RIGHT JUSTIFIED MODE

In right justified mode, the LSB of DIN1/2/3 is sampled by the WM8772EFT on the

rising edge of DACBCLK preceding a DACLRC transition. The LSB of the ADC data is

output on DOUT and changes on the falling edge of ADCBCLK preceding a ADCLRC

transition and may be sampled on the rising edge of ADCBCLK. ADCLRC and DACLRC

are high during the left samples and low during the right samples (

Figure 48).

LEFT CHANNEL

RIGHT CHANNEL

DACLRC/

ADCLRC

DACBCLK/

ADCBCLK

DIN1/2/3/

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 48 Right Justified Mode Timing Diagram

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