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WM8772SEDS/RV 데이터시트(PDF) 17 Page - Wolfson Microelectronics plc |
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WM8772SEDS/RV 데이터시트(HTML) 17 Page - Wolfson Microelectronics plc |
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17 / 73 page ![]() Production Data WM8772EDS – 28 LEAD SSOP w PD Rev 4.2 October 2005 17 BCLK (Output) DOUT LRC (Output) t DL DIN1/2/3 t DDA t DHT t DST Figure 15 Digital Audio Data Timing – Master Mode Test Conditions AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, TA = +25 oC, Master Mode, fs = 48kHz, MCLK = 256fs unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Audio Data Input Timing Information LRC propagation delay from BCLK falling edge tDL 0 10 ns DOUT propagation delay from BCLK falling edge tDDA 0 10 ns DIN1/2/3 setup time to BCLK rising edge tDST 10 ns DIN1/2/3 hold time from BCLK rising edge tDHT 10 ns Table 3 Digital Audio Data Timing – Master Mode |
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