WM8775SEDSSLASHR datasheet(18/39 Pages) WOLFSON

18 / 39 page

WM8775

Production Data

PD Rev 4.1, June 2006

LEFT CHANNEL

RIGHT CHANNEL

ADCLRC

BCLK

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

Figure 14 Right Justified Mode Timing Diagram

2S MODE

In I

2S mode, the MSB of the ADC data is output on DOUT and changes on the first falling edge of

BCLK following an ADCLRC transition and may be sampled on the rising edge of BCLK. ADCLRC is

low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

ADCLRC

BCLK

DOUT

1/fs

n-2 n-1

LSB

MSB

n-2 n-1

LSB

MSB

1 BCLK

Figure 15 I

2S Mode Timing Diagram

DSP MODE

In DSP/PCM mode, the left channel MSB is available on either the 1

st (mode B) or 2nd (mode A)

rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data

immediately follows left channel data. Depending on word length, BCLK frequency and sample rate,

there may be unused BCLK cycles between the LSB of the right channel data and the next sample.

In device master mode, the LRC output will resemble the frame pulse shown in Figure 16 and Figure

17. In device slave mode, Figure 18 and Figure 19, it is possible to use any length of frame pulse

less than 1/fs, providing the falling edge of the frame pulse occurs greater than one BCLK period

before the rising edge of the next frame pulse.

WM8775SEDS/R 데이터시트(PDF) 18 Page - Wolfson Microelectronics plc

WM8775SEDS/R 데이터시트(HTML) 18 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39

데이터시트 다운로드

링크 URL