WM8775

Production Data

w

PD Rev 4.1, June 2006

30

When the noise gate is triggered, the PGA gain is held constant (preventing it from ramping up as it

would normally when the signal is quiet).

The table below summarises the noise gate control register. The NGTH control bits set the noise

gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 6dB steps.

Levels at the extremes of the range may cause inappropriate operation, so care should be taken with

set–up of the function. Note that the noise gate only works in conjunction with the ALC function, and

always

operates

on

the

same

channel(s)

as

the

ALC

(left,

right,

both,

or

none).

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

0

NGAT

0

Noise gate function enable

1 = enable

0 = disable

R19(13h)

0010011

Noise Gate

Control

4:2

NGTH[2:0]

000

Noise gate threshold (with respect to

analogue input level)

000: -78dBFS

001: -72dBfs

… 6 dB steps

110: -42dBFS

111: -36dBFS

ADC INPUT MUX AND POWERDOWN CONTROL

REGISTER

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R21(15h)

0010101

ADC Mux and

Powerdown

Control

3:0

AMX[3:0]

0001

ADC input mixer control bits (see

Table 12)

Register bits AMX[3:0] control the left and right channel inputs into the stereo ADC. The default is

AIN1. One bit of AMX is allocated to each stereo input pair to allow the signals to be mixed before

being digitised by the ADC. For example, if AMX[3:0] is 0101, the input signal to the ADC will be

(AIN1L+AIN3L) on the left channel and (AIN1R+AIN3R) on the right channel.

However if the analogue input buffer is powered down, by setting AINPD, then all 4-channel mux

inputs are switched to buffered VMIDADC.

AMX[3:0]

LEFT ADC INPUT

RIGHT ADC INPUT

0001

AIN1L

AIN1R

0010

AIN2L

AIN2R

0100

AIN3L

AIN3R

1000

AIN4L

AIN4R

Table 12 ADC Input Mixer Control

AIN1L/R

AIN2L/R

AIN3L/R

AIN4L/R

AMX[0]

AMX[1]

AMX[2]

AMX[3]

Figure 24 ADC Input Mixer