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WM8955BLGECO/V 데이터시트(PDF) 13 Page - Wolfson Microelectronics plc |
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WM8955BLGECO/V 데이터시트(HTML) 13 Page - Wolfson Microelectronics plc |
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13 / 44 page ![]() Production Data WM8955BL w PD Rev 4.1 February 2007 13 Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information DACLRC propagation delay from BCLK falling edge tDL 10 ns DACDAT setup time to BCLK rising edge tDST 10 ns DACDAT hold time from BCLK rising edge tDHT 10 ns AUDIO INTERFACE TIMING – SLAVE MODE BCLK DACLRC t BCH t BCL t BCY DACDAT t LRSU t DS t LRH Figure 3 Digital Audio Data Timing – Slave Mode (see Control Interface) Test Conditions DBVDD = 3.3V, DGND = 0V, TA = +25 oC, Slave Mode fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT System Clock Timing Information BCLK cycle time tBCY 50 ns BCLK pulse width high tBCH 20 ns BCLK pulse width low tBCL 20 ns DACLRC setup time to BCLK rising edge tLRSU 10 ns DACLRC hold time from BCLK rising edge tLRH 10 ns DACDAT hold time from BCLK rising edge tDH 10 ns CONTROL INTERFACE TIMING – 3-WIRE MODE CSB SCLK SDIN t CSL t DHO t DSU t CSH t SCY t SCH t SCL t SCS LSB t CSS Figure 4 Control Interface Timing – 3-Wire Serial Control Mode |
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