WM8955BLGECOSLASHV datasheet(26/44 Pages) WOLFSON

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WM8955BL

Production Data

PD Rev 4.1 February 2007

DIGITAL AUDIO INTERFACE

The digital audio interface is used for feeding audio data into the WM8955BL. It uses three pins:

•

DACDAT: DAC data input

•

DACLRC: DAC data alignment clock

•

BCLK: Bit clock, for synchronisation

The clock signals BCLK and DACLRC can be outputs when the WM8955BL operates as a master, or

inputs when it is a slave (see Master and Slave Mode Operation, below).

Four different audio data formats are supported:

•

Left justified

•

Right justified

•

DSP mode

All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the

Electrical Characteristic section for timing information.

MASTER AND SLAVE MODE OPERATION

The WM8955BL can be configured as either a master or slave mode device. As a master device the

WM8955BL generates BCLK and DACLRC and thus controls sequencing of the data transfer on

DACDAT. In slave mode, the WM8955BL responds with data to clocks it receives over the digital

audio interface. The mode can be selected by writing to the MS control bit. Master and slave modes

are illustrated below.

BCLK

DACDAT

DACLRC

WM8955L

DAC

DSP /

DECODER

BCLK

DACDAT

DACLRC

WM8955L

DAC

DSP /

DECODER

Figure 10 Master Mode

Figure 11 Slave Mode

AUDIO DATA FORMATS

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a DACLRC

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each DACLRC

transition.

Figure 12 Left Justified Audio Interface (assuming n-bit word length)

In Right Justified mode, the LSB is available on the last rising edge of BCLK before a DACLRC

transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK

frequency and sample rate, there may be unused BCLK cycles after each DACLRC transition.

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