AT43USB355M-AC datasheet(26/115 Pages) ATMEL

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AT43USB355

2603G–USB–04/06

General Interrupt Mask Register – GIMSK

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the

external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in

the MCU general Control Register (MCUCR) defines whether the external interrupt is acti-

vated on rising or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an

interrupt request even if INT1 is configured as an output. The corresponding interrupt of Exter-

nal Interrupt Request 1 is executed from program memory address $004. See also “External

Interrupts” on page 29.

• Bit 6 – INT0: Interrupt Request 0 (Suspend/Resume Interrupt) Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the

external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in

the MCU general Control Register (MCUCR) defines whether the external interrupt is acti-

vated on rising or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an

interrupt request even if INT0 is configured as an output. The corresponding interrupt of Inter-

rupt Request 0 is executed from program memory address $002. See also “External

Interrupts” on page 29.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT43USB355 and always read as zero.

General Interrupt Flag Register – GIFR

• Bit 7 – INTF1: External Interrupt Flag1

When an event on the INT1 pin triggers an interrupt request, INTF1 becomes set (one). If the

I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the interrupt vec-

tor at address $004. The flag is cleared when the interrupt routine is executed. Alternatively,

the flag can be cleared by writing a logical one to it.

• Bit 6 – INTF0: Interrupt Flag0 (Suspend/Resume Interrupt Flag)

When an event on the INT0 (that is, a USB event-related interrupt) triggers an interrupt

request, INTF0 becomes set (one). If the I-bit in SREG and the INT0 bit in GIMSK are set

(one), the MCU will jump to the interrupt vector at address $002. The flag is cleared when the

interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bits 5..0 – Res: Reserved Bits

These bits are reserved bits in the AT43USB355 and always read as zero.

Bit

210

$3B ($5B)

INT1

INT0

–

GIMSK

Read/Write

R/W

Initial Value

Bit

543

$3A ($5A)

INTF1

INT F0

–

GIFR

Read/Write

R/W

Initial Value

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