AT43USB326 datasheet(60/102 Pages) ATMEL

60 / 102 page

AT43USB326

3313D–USB–04/06

Hardware clears this bit after it receives an ACK. If the interrupt is enabled and if the TX Com-

plete bit is set, clearing the TX Packet Ready bit by the hardware causes an interrupt to the

microcontroller.

•Bit 3 – STALL_SENT_ACK: Acknowledge Stall Sent Interrupt

Firmware sets this bit to clear STALL SENT, CSR bit 3. The 1 written in the CSRACK3 bit is

not actually stored and thus does not have to be cleared.

•Bit 2 – RX_SETUP_ACK: Acknowledge RX SETUP Interrupt

Firmware sets this bit to clear RX SETUP, CSR bit2. The 1 written in the CSRACK2 bit is not

actually stored and thus does not have to be cleared.

•Bit 1 – RX_OUT_PACKET_ACK: Acknowledge RX OUT PACKET Interrupt

Firmware sets this bit to clear RX OUT PACKET, CSR bit1. The 1 written in the CSRACK1 bit

is not actually stored and thus does not have to be cleared.

•Bit 0 – TX_COMPLETE_ACK: Acknowledge TX COMPLETE Interrupt

Firmware sets this bit to clear TX COMPLETE, CSR bit0. The 1 written in the CSRACK0 bit is

not actually stored and thus does not have to be cleared.

Function Endpoint 1,2 Service Routine Register – FCSR1,2

• Bit 7..4 – Reserved

These bits are reserved in the AT43USB326 and will read as zero.

• Bit 3 – STALL SENT

The USB hardware sets this bit after a STALL has been sent to the host. The firmware uses

this bit when responding to a Get Status[Endpoint] request. It is a read only bit and that is

cleared indirectly by writing a one to the STALL_SENT_ACK bit of the Control and Acknowl-

edge Register.

• Bit 2 – Reserved

This bit is reserved in the AT43USB326 and will read as zero.

• Bit 1 – RX OUT PACKET

The USB hardware sets this bit after it has stored the data of an OUT transaction in the FIFO.

While this bit is set, the hardware will NAK all OUT tokens. The USB hardware will not over-

write the data in the FIFO except for an early set-up. RX OUT Packet is used by a BULK OUT

or ISO OUT or INT OUT endpoint.

Setting this bit causes an interrupt to the microcontroller if the interrupt is enabled. FW clears

this bit after the FIFO contents have been read by writing a one to the RX_SETUP_ACK bit of

the Control and Acknowledge Register.

• Bit 0 – TX COMPLETE: Transmit Completed

This bit is used by the endpoint hardware to signal to the microcontroller that the IN transac-

tion was completed successfully. This bit is read only and is cleared indirectly by writing a one

to the TX_COMPLETE_ACK bit of the Control and Acknowledge Register.

Bit

765

Function EP1 $1FDC

–

STALL SENT

–

RX OUT PACKET

TX COMPLETE

FCSR1

Function EP2 $1FDB

–

STALL SENT

–

RX OUT PACKET

TX COMPLETE

FCSR2

Read/Write

Initial Value

AT43USB326 데이터시트(PDF) 60 Page - ATMEL Corporation

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