AT89LP2052 datasheet(48/90 Pages) ATMEL

48 / 90 page

3547F–MICRO–6/06

AT89LP2052/LP4052

20. Programmable Watchdog Timer

The programmable Watchdog Timer (WDT) protects the system from incorrect execution by trig-

gering a system reset when it times out after the software has failed to feed the timer prior to the

timer overflow. The WDT counts CPU clock cycles. The prescaler bits, PS0, PS1 and PS2 in

SFR WDTCON are used to set the period of the Watchdog Timer from 16K to 2048K clock

cycles. The WDT is disabled by Reset and during Power-down mode. When the WDT times out

without being serviced, an internal RST pulse is generated to reset the CPU. See Table 20-1 for

the available WDT period selections.

Note:

*The WDT time-out period is dependent on the system clock frequency.

The Watchdog Timer consists of a 14-bit timer with 7-bit programmable prescaler. Writing the

sequence 1EH/E1H to the WDTRST register enables the timer. When the WDT is enabled, the

WDTEN bit in WDTCON will be set to “1”. To prevent the WDT from generating a reset when if

overflows, the watchdog feed sequence must be written to WDTRST before the end of the time-

out period. To feed the watchdog, two write instructions must be sequentially executed success-

fully. Between the two write instructions, SFR reads are allowed, but writes are not allowed. The

instructions should move 1EH to the WDTRST register and then 1EH to the WDTRST register.

An incorrect feed or enable sequence will cause an immediate watchdog reset. The program

sequence to feed or enable the watchdog timer is as follows:

MOV WDTRST, #01Eh

MOV WDTRST, #0E1h

Table 20-1.

Watchdog Timer Time-out Period Selection

WDT Prescaler Bits

Period*

(Clock Cycles)

PS2

PS1

PS0

000

16K

001

32K

010

64K

011

128K

100

256K

101

512K

1024K

2048K

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