2

3633C–DFLASH–08/06

AT26DF321 [Preliminary]

The AT26DF321 also offers a sophisticated method for protecting individual sectors against

erroneous or malicious program and erase operations. By providing the ability to individually pro-

tect and unprotect sectors, a system can unprotect a specific sector to modify its contents while

keeping the remaining sectors of the memory array securely protected. This is useful in applica-

tions where program code is patched or updated on a subroutine or module basis, or in

applications where data storage segments need to be modified without running the risk of errant

modifications to the program code segments. In addition to individual sector protection capabili-

ties, the AT26DF321 incorporates Global Protect and Global Unprotect features that allow the

entire memory array to be either protected or unprotected all at once. This reduces overhead

during the manufacturing process since sectors do not have to be unprotected one-by-one prior

to initial programming.

Specifically designed for use in 3-volt systems, the AT26DF321 supports read, program, and

erase operations with a supply voltage range of 2.7V to 3.6V. No separate voltage is required for

programming and erasing.

2.

Pin Descriptions and Pinouts

Table 2-1.

Pin Descriptions

Symbol

Name and Function

Asserted

State

Type

CS

CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the

device will be deselected and normally be placed in standby mode (not Deep Power-Down mode),

and the SO pin will be in a high-impedance state. When the device is deselected, data will not be

accepted on the SI pin.

A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition

is required to end an operation. When ending an internally self-timed operation such as a program

or erase cycle, the device will not enter the standby mode until the completion of the operation.

Low

Input

SCK

SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the flow of

data to and from the device. Command, address, and input data present on the SI pin is always

latched on the rising edge of SCK, while output data on the SO pin is always clocked out on the

falling edge of SCK.

Input

SI

SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data input

including command and address sequences. Data on the SI pin is always latched on the rising

edge of SCK.

Input

SO

SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin is

always clocked out on the falling edge of SCK.

Output

WP

WRITE PROTECT: The WP pin controls the hardware locking feature of the device. Please refer to

“Protection Commands and Features” on page 11 for more details on protection features and the

WP pin.

The WP pin is internally pulled-high and may be left floating if hardware controlled protection will

not be used. However, it is recommended that the WP pin also be externally connected to V

CC

whenever possible.

Low

Input

V

CC

Operations at invalid V

Power

GND

GROUND: The ground reference for the power supply. GND should be connected to the system

ground.

Power