AT83SND1CXXX-ROTIL datasheet(18/212 Pages) ATMEL

18 / 212 page

4109J–8051–10/06

AT8xC51SND1C

Figure 6-2.

AT80C51SND1C Memory Architecture

6.1.1

User Space

This space is composed of a 64K Bytes code (Flash, EEPROM, EPROM…) memory. It contains

the user’s application code.

6.1.2

Memory Interface

The external memory interface comprises the external bus (port 0 and port 2) as well as the bus

control signals (PSEN, and ALE).

Figure 6-3 shows the structure of the external address bus. P0 carries address A7:0 while P2

carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 6-3 describes the exter-

nal memory interface signals.

Figure 6-3.

External Code Memory Interface Structure

FFFFh

64K Bytes

External Memory

0000h

User

Table 20. External Code Memory Interface Signals

Signal

Name

Type

Description

Alternate

Function

A15:8

Address Lines

Upper address lines for the external bus.

P2.7:0

AD7:0

I/O

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

P0.7:0

ALE

Address Latch Enable

ALE signals indicates that valid address information are available on lines

AD7:0.

PSEN

Program Store Enable Output (AT80C51SND1C Only)

This signal is active low during external code fetch or external code read

(MOVC instruction).

Flash

EPROM

AT80C51SND1C

AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

Latch

PSEN

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