AT83SND1CXXX-ROTIL datasheet(19/212 Pages) ATMEL

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4109J–8051–10/06

AT8xC51SND1C

6.1.3

External Bus Cycles

This section describes the bus cycles the AT80C51SND1C executes to fetch code (see

Figure 6-4) in the external program/code memory.

External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock peri-

ods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2

mode see section “Clock “.

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and

does not provide precise timing information.

For bus cycling parameters refer to the ‘AC-DC parameters’ section.

Figure 6-4.

External Code Fetch Waveforms

6.2

ROM Memory Architecture

As shown in Figure 6-5 the AT83SND1C ROM memory is composed of one space detailed in

the following paragraph.

Figure 6-5.

AT83SND1C Memory Architecture

6.2.1

User Space

This space is composed of a 64K Bytes ROM memory programmed during the manufacturing

process. It contains the user’s application code.

6.3

Flash Memory Architecture

As shown in Figure 6-6 the AT89C51SND1C Flash memory is composed of four spaces detailed

in the following paragraphs.

ALE

PSEN

PCL

PCH

PCL

D7:0

PCH

D7:0

CPU Clock

FFFFh

64K Bytes

ROM Memory

0000h

User

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