ATAM862 datasheet(30/110 Pages) ATMEL

30 / 110 page

4554E–4BMCU–05/06

ATAM862-3

Figure 19-7. 32-kHz Crystal Oscillator

Note:

Both, the 4-MHz and the 32-kHz crystal oscillator, use an integrated 14 stage divider circuit to sta-

bilize oscillation before the oscillator output is used as system clock. This results in an additional

delay of about 4 ms for the 4-MHz crystal and about 500 ms for the 32-kHz crystal.

19.3

Clock Management

The clock management register controls the system clock divider and synchronization stage.

Writing to this register triggers the synchronization cycle.

19.3.1

Clock Management Register (CM)

Auxiliary register address: "3"hex

Table 19-3.

Core Speed Select

32-kHz

oscillator

32Out

OSC1

OSC2

Oscin

Oscout

XTAL

32 kHz

Configurable

Bit 3

Bit 2

Bit 1

Bit 0

CM:

NSTOP

CCS

CSS1

CSS0

Reset value: 1111b

NSTOP

Not STOP peripheral clock

NSTOP = 0, stops the peripheral clock while the core is in SLEEP mode

NSTOP = 1, enables the peripheral clock while the core is in SLEEP mode

CCS

Core Clock Select

CCS = 1, the internal RC-oscillator 1 generates SYSCL

CCS = 0, the 4-MHz crystal oscillator, the 32-kHz crystal oscillator, an external clock

source or the internal RC-oscillator 2 with the external resistor at OSC1 generates SYSCL

dependent on the setting of OS0 and OS1 in the system configuration register

CSS1

Core Speed Select 1

CSS0

Core Speed Select 0

CSS1

CSS0

Divider

Note

Reset value

104

012

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