May 8, 2006 25692A2

Am29BDS643G

45

D A TA

SH EE T

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25

programming typicals assume checkerboard pattern.

3. The typical chip programming time is considerably less than the maximum chip programming time listed.

4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 10 for further information on command definitions.

6. The device has a minimum erase and program cycle endurance of 1 million cycles.

DATA RETENTION

Parameter

Typ (Note 1)

Max (Note 2)

Unit

Comments

Sector Erase Time

32 Kword

0.4

5

s

Excludes 00h programming

prior to erasure (Note 4)

8 Kword

0.4

5

Chip Erase Time

54

s

Word Programming Time

11.5

210

µs

Excludes system level

overhead (Note 5)

Accelerated Word Programming Time

4

120

µs

Chip Programming Time (Note 3)

48

144

s

Excludes system level

overhead (Note 5)

Accelerated Chip Programming Time

16

48

s

Parameter

Test Conditions

Min

Unit

Minimum Pattern Data Retention Time

150

°C10

Years

125

°C20

Years